Testbench and Verification for a 2×2-Bit Multiplier Module

Optimized Logic for a Compact 2×2-Bit Multiplier Circuit

A 2×2-bit multiplier multiplies two 2-bit unsigned binary numbers (A1A0 × B1B0) producing a 4-bit product (P3 P2 P1 P0). Because inputs are small, you can implement the multiplier with minimal gates by exploiting common subexpressions and simple carry logic.

Truth and partial products

• Partial products:
  • p0 = A0 & B0 → directly P0.
  • p1 = A1 & B0
  • p2 = A0 & B1
  • p3 = A1 & B1
• Product bits:
  • P0 = p0
  • P1 = p1 XOR p2
  • Carry to next bit c1 = p1 & p2
  • P2 = p3 XOR c1
  • P3 = p3 & c1 (for unsigned 2×2, P3 = p3 & c1 is equivalent to p3 AND carry; note p3 may also directly form P3 when carries propagate)

Minimal gate implementation

• Generate the four AND gates for p0–p3.
• Use one XOR and one AND to compute P1 and its carry: P1 = p1 ⊕ p2; c1 = p1 & p2.
• Use one XOR for P2: P2 = p3 ⊕ c1.
• Compute P3 as p3 & c1 (single AND).
• Total gate count (excluding inverters): 4 ANDs (partial products) + 1 XOR + 1 AND (for c1) + 1 XOR + 1 AND = 8 basic gates; some XORs can be built from NAND/NOR depending on library.

Optimizations and alternatives

• Wallace or Dadda trees are overkill for 2×2; simple carry-save ideas reduce propagation but add gates.
• If area is critical, use shared gates or implement XOR as XNOR+INV depending on cell availability.
• For speed-critical design, implement P1 with a full-adder style: sum = p1 ⊕ p2, carry = p1 & p2 — this minimizes logic depth.
• For FPGA, use LUTs to implement the whole multiplier in a single LUT if available (one 4-input LUT can implement all outputs with optimized logic).
• For signed multiplication (2’s complement), adjust partial-product generation and sign-extension; a small adder handles sign bits.

Verification tips

• Exhaustively simulate all 16 input combinations; compare outputs to A×B expected decimal values.
• Create a simple testbench that iterates A=0..3, B=0..3 and checks product bits.

When to use this design

• Educational circuits, tiny arithmetic units, configurable logic blocks, or as a building block in larger multipliers where compact and fast small multipliers are needed.

If you want, I can provide a Verilog module, gate-level schematic, or a 4-LUT implementation for this optimized 2×2 multiplier.